Random access read/write memory devices are generally assembled from a matrix or other grouping of memory cells. Each such cell is capable of storing one binary digit, or bit, of information. A conventional prior art RAM device has the form generally illustrated in FIG. 1, wherein each memory cell MC.sub.xy (where x and y are indices in a two-dimensional matrix) is connected to a pair of conductors B.sub.x and B*.sub.x. The conductors B.sub.x and B*.sub.x are typically called bit lines, bit-sense lines, or bit buses. In the figure, a portion of a column of the matrix is shown for the value x=i, from rows y=j through y=j+n-1. Bit lines B.sub.x and B*.sub.x normally carry signals of complementary values imposed by a differential output stage in, for example, a write amplifier or memory cell. For reading the contents of a cell, a differential voltage representing those contents is provided via bit lines B.sub.x and B*.sub.x to a sense amplifier 10. The conventional sense amplifier typically has a differential input stage to receive the signals imposed on the bit lines and a double-ended (i.e., differential) output for driving subsequent amplifier stages.
Sense amplifier design has a substantial impact on the performance of a RAM. The two most important characteristics of a RAM influenced by its sense amplifiers are the speed of a read operation and the power consumption of the device. Often, these two factors work against each other; more power is frequently required when faster switching speed is desired of an amplifier. A good sense amplifier, though, should switch states rapidly, draw little power, be reliable and be inexpensive to produce.
Noise immunity is also very much dependent on sense amplifier design. A sense amplifier should operate over a wide range of input voltages and be minimally sensitive to power supply fluctuations and common mode signals appearing on the bit lines, while being maximally sensitive (i.e., provide high gain) to differential signals appearing on those same conductors.
Minimization of sense amplifier power consumption during quiescent conditions is particularly important. At any instant, a typical RAM chip or array of chips will usually have very few sense amplifiers engaged in switching compared to the number of sense amplifiers sitting idly under quiescent conditions. Therefore, if the RAM chip is to dissipate only a small amount of power, quiescent current drain by the sense amplifiers must be minimized.
Many designs have been proposed for MOS sense amplifiers and many techniques have been advocated for providing faster, lower-power-consumption sense amplifiers. Among these techniques are bit line equalization (pre-charging) and address transition detection. The prior art also includes sense amplifiers using complementary MOSFET devices on both sides of a differential amplifier, with gate inputs configured to effect voltage swing without providing a high conductance current path and the use of shunt-connected devices driven by complementary outputs in place of active load resistances, to improve common mode rejection. Further, the art includes the use of a number of feedback arrangements to improve switching speed and other characteristics.
These various improvements are achieved in the prior art at the expense of increasing the number of components in each sense amplifier, generally with an attendant increase in the area of the semiconductor required for each sense amplifier and possibly consuption of unnecessary power.
Therefore, it is an object of the present invention to provide an improved sense amplifier.
Another object of the invention is to provide a sense amplifier which reduces power dissipation and still provides high speed operation.